1. Field of the Invention
The present invention relates generally to asynchronous data transport across a network system. More particularly, the present invention pertains to a method and system for scheduling multiple channel data output to restore timing to the data flow in each channel and to optimize the buffering requirements of each channel.
2. Related Art
Data networks such as LANs (local area networks) and WANs (wide area networks) have become commonplace in contemporary business and industry. Such networks allow communication between data stations in various locations. See, e.g. the LAN systems described by Tangney et al., Local Area Networks and Their Applications, (Prentice Hall: UK 1988) and Martin et al., Local Area Networks Architectures and Implementations, (Prentice Hall: USA 1989) (both of which are incorporated by reference herein).
A complex local area network or a wide area data network typically involves many independent systems and distant network locations. For example, fiber optic data networks are used to transport customer data within a city or across a continent. Maintaining a consistent reference time between these independent systems and remote portions of such a data network is especially difficult.
In addition, many applications such as constant bit rate (CBR) applications are particularly sensitive to temporal distortions of data. For instance, a constant bit rate is essential in digitized speech and voice communications, circuit emulation, video teleconferencing, and telemetry. In a broadband integrated services digital network (BISDN), asynchronous transport of multi-channel data at constant bit rates throughout a data network is needed to implement video teleconferencing.
Synchronous (clocked) and asynchronous (not clocked) transport modes are known for governing the flow of data through a network. See, e.g., the discussion of synchronous (clocked) and asynchronous (not-clocked) busses discussed in Hennessy, J. L. and Patterson, D. A., "Computer Architecture: A Quantitative Approach," Morgan Kaufmann Publishers (San Mateo, Calif.), 1990, and in U.S. Pat. No. 4,494,194 issued to Harris et al. (both of which are incorporated by reference herein). In synchronous systems, a separate clock control line is required. All data must be run at the same clock rate. Clock skew further limits the length of the network data bus. Synchronous schemes are thus best suited for well-defined, short-distance data communication applications such as a CPU-memory bus.
Under an asynchronous scheme, no separate clock line is used, but self-timed protocols must accompany data transported across the network. In asynchronous transport mode protocols (ATM), timing information is often embedded within a frame format. For instance, the preamble or header field can contain timing stamps or other timing related information to allow the bit rate for outputting data to be established at receivers downstream in the data network regardless of cell clumping or the particular input data rate. In this manner, a cell receiver can adapt to a variety of input data rates. Reserving bits for timing information, however, increases overhead and reduces data transmission efficiency.
In asynchronous transport mode, cells of data can also arrive in "bursts." Greater buffering capacity is then required to accommodate the irregular data transmission. Gaps can also occur between packets and the channel data therein which leads to further delay and temporal distortion of network data.
Unlike ATM applications, packet switching technology uses large channel packets rather than individual cells of data. Multiplexers are used to send channel packets from multiple channels between a source and destination node of a network. Demultiplexers then separate the channel packets into their respective separate channels.
In such packet switching technology, a constant output rate has been established without using timing stamps in an asynchronous demultiplexer for a packetized multiple channel data stream. See, the U.S. Pat. No. 5,398,241 issued to applicant on Mar. 14, 1995, and incorporated herein by reference. In the '241 patent, the slower output bit rate for 2048-bit packets of information from the demultiplexer is generated based on the packet arrival frequency for each channel and the output FIFO fullness for that channel. In the context of a packet demultiplexer, however, the output of a data channel is effectuated independent of the other channels. Coordination or scheduling in the data output between channels is not relevant in the '241 patent demultiplexer environment.
What is desired, then, is a multi-channel asynchronous data transport system and method which can schedule data output between channels while still allowing each channel to adapt to variable input data rates and to provide a substantially constant bit rate output. This constant bit output rate needs to be obtained regardless of preceding temporal distortion in the data network, i.e. "cell clumping," and without requiring cells to carry time stamps or other timing information.
In addition, it is desirable to reduce the occurrence of gaps in the multiple channel data stream and to lower system buffering requirements.